In recent years, image pickup devices operate at increasingly higher frequencies due to an improvement in performance. Outputs from the image pickup devices are made irrespective of the operation of an image signal processor (ISP) provided in the subsequent stage, however, a conventional ISP is limited in increasing the operating frequency to process inputs from the image pickup devices in real time, due to the performance limitations of its memory in terms of the operating frequency.
In view of this problem, there has been proposed a technique in which, as for pixel data read from image pickup devices in order of raster scanning, an ISP receives, at a time, the pixel data corresponding to a plurality of pixels and processes the received pixel data in parallel, to thereby reduce the operating frequency in the ISP.
Note however that by simply outputting, in parallel, the pixel data received in sets of a plurality of pixels input in raster scan order from the image pickup devices, the data output in parallel does not appear in the raster scan order but appears in a skipping sequence of the raster scan order with an interval. This condition does not allow parallel processing taking place in a subsequent circuit. Therefore, using line buffers, for example, the parallel data in the skipping sequence needs to be reordered so as to allow the parallel processing in the subsequent circuit.
Japanese Laid-open Patent Publication No. 8-96116
Japanese Laid-open Patent Publication No. 2001-67265
In the case of processing N pixels in parallel, N line buffers (random access memories (RAM), for example) may be used. As described above, outputs (reads) from the image pickup devices are made one after another irrespective of the operation of the ISP. In view of this, it is desired that, at the completion of data writes of N lines, reads allowing a write area for the next line to be secured have been completed. In order to do this, the reads may be carried out simultaneously with writes of the N-th line.
However, if the number of pixels to be processed in parallel (hereinafter, simply referred to as the ‘parallel number’) increases in this processing scheme, data writes of a new line may occur at addresses where reads of a previous line have yet to be completed, thereby overwriting and thus corrupting data of the previous line. One way to prevent such data corruption is to provide more than N line buffers, however, this results in an increase in the circuit area.